The present invention generally relates to a database for use in the design of an integrated circuit device and to a design process using such a database. More particularly, the present invention relates to methods of designing a very-large-scale integrated circuit device such as a system LSI even more efficiently.
In the prior art, an integrated circuit device is normally designed by generating blocks (or cores), which will be eventually replaced with actual components, through the specification design, architectural (or behavioral) design and register-transfer (RT) levels and then logically synthesizing these blocks together. These blocks are created through a top-down design approach, i.e., from the highest-order specification design level down to the lowermost RT level.
FIG. 16 is a flowchart illustrating the flow of a common design process of an LSI. At the specification design level, the designer defines a design specification empirically using some computer-aided design tool. At this early stage, it is not clear even for him or her whether or not the system will actually work in accordance with the specification defined. When this specification or architectural design is completed, tests (or simulations) are often carried out to see if the virtual system, made to the specification defined, will function properly just as intended. Once good test results are obtained, the system is further analyzed for its performance at the lowermost RT level. This analysis is usually carried out on a block-by-block basis. So if at least one of the building blocks of the system is found optimum, then the block is adopted. If there are no such blocks, however, the design process should return to the start of the loop to re-design an operable system over again. By repeatedly performing these process steps, the system being designed is refined little by little, and an optimum system can be constructed in the end.
According to this method, however, it would take an enormous amount of time to design a very-large-scale integrated circuit, like a system LSI, if the designer imposes overly rigorous requirements (i.e., specification excessively hard to realize) on the integrated circuit being designed at a higher level of the design process. This is because a system LSI includes a huge number of components that should be laid out in a very complicated manner. Thus, in the known process, the design loop should be reiterated too many times to complete the design process in a reasonable amount of time. Or in the worst-case scenario, the design process might sometimes reach a deadlock.
As is often the case, common designers are apt to overdesign, or expect highest possible performance at first, although so severe a specification is not actually needed. In fact, it is not until the lower-level design has reached a deadlock that the designers relax their requirements. Thus, those unrealistic performance requirements will constitute a great obstacle to the efficient design of a system LSI, which usually needs a huge workload even for the design of a single block.
It is therefore an object of the present invention to provide a database and design method that can avoid the needless, lengthy exploration of numerous architectural choices or the design deadlock by making those requirements as realistic as possible at the start of a design process.
A first inventive database stores thereon data needed in designing an integrated circuit device that will be made up of a plurality of components. The database includes: a virtual core (VC) cluster, on which the data needed in designing the components is separately stored at least on a specification VC and a register-transfer-level VC (RTL-VC); and implementability evaluation information stored on the specification VC. The information represents performance of the RTL-VC in accordance with a specification defined by the specification VC in the VC cluster.
According to the present invention, it is possible to provide a database, which is effectively applicable to determining, at the specification level (i.e., the highest level of a design process), whether or not the integrated circuit device will be able to meet the required performance easily.
In one embodiment of the present invention, the implementability evaluation information may contain data about at least one of processing time, layout area, power dissipation and test cost.
In another embodiment of the present invention, the implementability evaluation information may contain data about at least a processing time and a time needed for inputting or outputting data. In such an embodiment, the processing time, including a time needed for transferring data, can be used as a performance parameter for the implementability evaluation.
In still another embodiment, if there are multiple RTL-VCs associated with the specification, then the implementability evaluation information may contain the data as at least one of minimum, average, maximum and optimum values that are parameters representing the performance of each said RTL-VC.
In yet another embodiment, the first inventive database may further include workload estimation information stored on the specification VC. The information represents a workload needed for newly developing a VC in accordance with the specification and a workload needed for reusing the VC in accordance with the specification.
A second inventive database also stores thereon data needed in designing an integrated circuit device that will be made up of a plurality of components. The database includes: a virtual core (VC) cluster, on which the data needed in designing the components is separately stored at least on a specification VC and a register-transfer-level VC (RTL-VC); and workload estimation information stored on the specification VC. The information represents a workload needed for newly developing a VC in accordance with the specification defined by the specification VC and a workload needed for reusing the VC in accordance with the specification.
According to the present invention, a workload needed for a design process can be estimated with certain accuracy at the highest level of the design process. Thus, the number of designers needed, for example, can be known in advance by taking the estimated workload and the due date into account.
In the first or second inventive database, the specification VC may be combined with an architecture VC to form a single specification/architecture VC.
An inventive method is adapted to design an integrated circuit device, which will be made up of a plurality of components, using a database. The database includes: a virtual core (VC) cluster, on which the data needed in designing the components is separately stored at least on a specification VC and a register-transfer-level VC (RTL-VC); and implementability evaluation information stored on the specification VC. The information represents performance of the RTL-VC in accordance with a specification defined by the specification VC. The method includes the steps of: a) entering the specification VCs corresponding to the respective components; and b) evaluating the implementability of the integrated circuit device being designed using the specification VCs entered in accordance with the implementability evaluation information stored on the specification VCs.
According to the inventive method, it is possible to expect, at the highest level of a design process of an integrated circuit device, whether or not the respective VCs will be able to meet the required performance easily. Thus, the needless, lengthy exploration of architectural alternatives or the design deadlock, which usually results from the overly rigorous requirements, is avoidable. As a result, even a very-large-scale integrated circuit device can be designed easily.
In one embodiment of the present invention, the implementability evaluation information may contain data about at least one of processing time, layout area, power dissipation and test cost. In that case, the step b) is preferably performed with at least one of the processing time, layout area, power dissipation and test cost used as a parameter.
In another embodiment of the present invention, the implementability evaluation information may contain data about at least a processing time and a time needed for inputting or outputting data. In that case, the step b) is preferably performed with a time needed for transferring data and the processing time used as parameters.
In still another embodiment, the implementability evaluation information may contain the data as at least one of minimum, average, maximum and optimum values that are parameters representing the performance of each said RTL-VC. In that case, the step b) is preferably performed based on at least one of the minimum, average, maximum and optimum values of the parameters.
In yet another embodiment, the step b) may be performed by comparing a required value of the performance of the VCs to an estimated value of the performance. The estimated value is derived from the implementability evaluation information stored on the specification VCs.
In this particular embodiment, the step b) is preferably performed with the estimated performance value of the VCs evaluated by percentage on the supposition that the required performance value is 100%. In this manner, the implementability can be evaluated based on not only the designer""s experience but also some objective criteria.
In an alternative embodiment, the step b) may also be performed with one of the VCs that has the lowest implementability extracted as a bottleneck as for a performance. In this manner, VCs to be newly developed and VCs that should have their requirements relaxed can be known clearly. Thus, the re-design process can be carried out smoothly at the highest level.
In still another embodiment, in the step b), reusable ones of the components may be provided with the performance of the RTL-VCs, corresponding to the components, in the VC cluster, while the other components may be provided with the performance defined by the implementability evaluation information stored on the specification VCs, corresponding to the components, in the VC cluster. In this manner, the implementability can be evaluated very easily.
In yet another embodiment, if a function model with exemplary design realizations is reused and part of the components of the model are changed to make a modified function model, then reusable ones of the components are provided in the step b) with the performance of the RTL-VCs in the VC cluster that has been applied to the exemplary design realizations. In this manner, the implementability can also be evaluated very easily.
In yet another embodiment, the method may further include the step of dividing the required performance value into multiple values, which have been weighted for the respective VCs corresponding to the components, after the step b) has been performed. In such an embodiment, the performance to be attained by each VC at the lowest level of a design process can be clarified and therefore the lowest-level design process can be carried out more quickly.
In yet another embodiment, the method may further include the step of equally dividing the required performance value for the respective VCs corresponding to the components after the step b) has been performed.
In yet another embodiment, workload estimation information may be further stored on the specification VCs of the database. The information represents a workload needed for newly developing a VC in accordance with the specification and a workload needed for reusing the VC in accordance with the specification. In that case, the method may further include the step of estimating a workload needed for each said component by reference to the workload estimation information stored on the specification VCs corresponding to the respective components after the step of dividing has been performed. In this manner, the due date of a design process, for example, can be managed smoothly.
In still another embodiment, the method may further include the step of dividing the required performance value for the respective VCs between the steps a) and b). In that case, the step b) may be performed by determining, in accordance with the implementability evaluation information stored on the specification VCs corresponding to the respective components, whether or not realizations, meeting the divided performance values, account for a predetermined percentage or more.
In yet another embodiment, the required performance value may be divided into multiple values weighted for the respective VCs.
Alternatively, the required performance value may be equally divided for the respective VCs.
In this particular embodiment, the step b) may also be performed with one of the VCs that has the lowest implementability extracted as a bottleneck as for a performance.
In yet another embodiment, workload estimation information may be further stored on the specification VCs of the database. The information represents a workload needed for newly developing a VC in accordance with the specification and a workload needed for reusing the VC in accordance with the specification. In that case, the method may further include the step of estimating a workload needed for each said component by reference to the workload estimation information, stored on the specification VCs corresponding to the respective components, after the step b) has been performed.